The present invention relates to etching chambers used in the etching of material layers on a semiconductor wafer substrate to fabricate semiconductor integrated circuits on the substrate. More particularly, the present invention relates to a thermocoupled lift pin system for measuring the backside temperature of a semiconductor wafer substrate after an etching process in order to prevent thermal cracking of the substrate upon subsequent transfer of the substrate from a high-temperature etching chamber to a lower-temperature loadlock or cooldown chamber.
In the semiconductor production industry, various processing steps are used to fabricate integrated circuits on a semiconductor wafer. These steps include deposition of a conducting layer on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal interconnection pattern, using standard lithographic techniques; subjecting the wafer substrate to a dry etching process to remove the conducting layer from the areas not covered by the mask, thereby etching the conducting layer in the form of the masked pattern on the substrate; removing or stripping the mask layer from the substrate typically using reactive plasma and chlorine gas, thereby exposing the top surface of the conductive interconnect layer; and cooling and drying the wafer substrate by applying water and nitrogen gas to the wafer substrate.
FIG. 1 illustrates a typical conventional wafer processing station 10 such as a Mattson ASPEN-III plasma etcher used in etching material layers on semiconductor wafers 14. The processing station 10 typically includes a loading port 13 which receives a front open unified cassette pod (FOUP) 12 from an automatic guided vehicle (AGV), overhead transport (OHT) vehicle or other pod transfer vehicle (not illustrated) in the cleanroom. A robot or other wafer transfer device 20 unloads the wafers 14 from the FOUP 12 and transfers the wafers 14 through a wafer transfer chamber 18 to a load lock/cool down chamber 22. A wafer transfer robot 26 in a wafer transfer chamber 24 transfers the wafers 14 from the load lock/cool down chamber 22 to a process chamber 28.
The wafer transfer robot 26 positions each wafer 14 on a corresponding set of multiple wafer lift pins 32 which are upwardly extended from a heater block 30 contained inside the process chamber 28, as illustrated in FIG. 2. The lift pins 32 are vertically slidably disposed in respective lift pin openings (not illustrated) in the heater block 30 and contact the bottom surface or backside of the wafer 14 in order to lower the wafer 14 to rest on the heater block 30 prior to the etching process and also lift the wafer 14 from the heater block 30 after the etching process. Raising and lowering of the lift pins 32 is facilitated by operation of a lift pin drive assembly (not illustrated). In the process chamber 28, the heater block 30 heats the wafer 14 to temperatures typically in the range of about 200xc2x0 C.-250xc2x0 C. during the etching process as reactive plasma or reactive gases such as chlorine are used to etch the unmasked conductive layer or layers from each wafer.
After completion of the etching process, the wafer transfer robot 26 transfers the wafers 14 from each process chamber 28 back to the load lock/cool down chamber 22, where the wafers 14 are cooled to a temperature of typically about 17xc2x0 C. Finally, the cooled wafers 14 are loaded on the wafer transfer robot or devices 20 in the wafer transfer chamber 18 and transferred to a front open unified cassette pod (FOUP) 16 at an unloading port 17, where the wafers 14 are removed from the wafer processing station 10 for subsequent transfer of the wafers 14 to another processing station or tool (not illustrated) in the clean room.
One of the problems inherent in the conventional method of cooling the wafers 14 in the low-temperature load lock/cool down chamber 22 after transfer of the wafers 14 from the high-temperature process chamber 28 is that the large disparity in temperatures between the chambers induces rapid cooling of the wafers 14, and the resulting thermal stresses tend to crack and damage the wafers 14. Such thermal stressing and damage to the wafers 14 significantly diminishes wafer throughput and adversely affects the efficiency of the entire semiconductor production process. Accordingly, a system is needed for measuring the temperature of the wafer before transfer of the wafer from the processing chamber to the load lock/cool down chamber and partially cooling the wafer before the transfer in order to prevent potentially damaging thermal stressing of the wafer.
An object of the present invention is to provide a system for measuring the temperature of an object before transfer of the object from a high-temperature environment to a low-temperature environment in order to prevent or reduce thermal stressing of the object.
Another object of the present invention is to provide a system for measuring the temperature of an object and lowering the temperature of the object as needed before transfer of the object from a high-temperature environment to a low-temperature environment in order to prevent or reduce thermal stressing of the object.
Still another object of the present invention is to provide a system which measures the temperature of an object and automatically lowers the temperature of the object prior to transferring the object to a high-temperature environment to a low-temperature environment in order to prevent or reduce thermal stressing of the object.
Yet another object of the present invention is to provide a system which utilizes a purge gas to lower the temperature of a processing chamber prior to transfer of a semiconductor wafer substrate from the processing chamber to a low-temperature cooling chamber in order to prevent or reduce thermal stressing of the wafer.
A still further object of the present invention is to provide a method of improving throughput of semiconductors in a semiconductor processing facility by preventing or substantially reducing the incidence of wafer-cracking or thermal stressing of the wafers during etching operations.
Another object of the present invention is to provide a system which utilizes thermocoupled lift pins to lower semiconductor wafers onto a heater block preparatory to an etching process in an etching chamber, raise the wafers from the heater block after the etching process, and measure the temperature of the wafers after the etching process in order to activate a wafer-cooling mechanism in the etching chamber in the event that the temperature of the wafer exceeds a predetermined temperature threshold.
In accordance with these and other objects and advantages, the present invention is a thermocoupled lift system for semiconductor etch chambers. The system comprises multiple thermocoupled lift pins which are vertically extendible from a heater block inside a semiconductor etch chamber and are capable of lowering a semiconductor wafer onto the heater block before the etching process and lifting the wafer from the heater block after the etching process. In the event that the temperature of the wafer exceeds a predetermined value after the etching process, the lift pins trigger release of a cooling purge gas such as nitrogen into the etching chamber to partially cool the wafer prior to transfer of the wafer to a cool down chamber for further cooling. The initial gas-induced cooling of the wafer prevents thermal stressing thereof upon transfer of the wafer to the cool down chamber.